CPC H03F 1/0233 (2013.01) [H03F 1/0227 (2013.01); H03F 1/3241 (2013.01); H03F 1/3258 (2013.01); H03F 1/56 (2013.01); H03F 3/195 (2013.01); H03F 3/21 (2013.01); H03F 3/245 (2013.01); H03F 2200/102 (2013.01); H03F 2200/105 (2013.01); H03F 2200/451 (2013.01); H03F 2201/3209 (2013.01)] | 16 Claims |
1. Envelope synchronization circuitry comprising:
a target voltage input at which a target voltage is provided;
an inverted target voltage input at which an inverted version of the target voltage is provided;
an operational amplifier comprising an inverting input, a non-inverting input coupled to a fixed potential, and an output at which an adjusted target supply voltage is provided;
a first adjustable resistor coupled between the target voltage input and the inverting input of the operational amplifier;
a second adjustable resistor coupled between the inverting input of the operational amplifier and the output of the operational amplifier;
a capacitor coupled between the inverting input and an intermediate node;
a first switch coupled between the intermediate node and the target voltage input; and
a second switch coupled between the inverted target voltage input and the intermediate node.
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