US 11,923,464 B2
Schottky barrier diode
Kohei Sasaki, Saitama (JP); Daiki Wakimoto, Saitama (JP); Yuki Koishikawa, Saitama (JP); and Quang Tu Thieu, Saitama (JP)
Assigned to Tamura Corporation, Tokyo (JP); and Novel Crystal Technology, Inc., Saitama (JP)
Appl. No. 16/628,078
Filed by TAMURA CORPORATION, Tokyo (JP); and Novel Crystal Technology, Inc., Saitama (JP)
PCT Filed Jun. 12, 2018, PCT No. PCT/JP2018/022297
§ 371(c)(1), (2) Date Jan. 2, 2020,
PCT Pub. No. WO2019/009021, PCT Pub. Date Jan. 10, 2019.
Claims priority of application No. 2017-132565 (JP), filed on Jul. 6, 2017.
Prior Publication US 2021/0151611 A1, May 20, 2021
Int. Cl. H01L 29/872 (2006.01); H01L 29/24 (2006.01); H01L 29/47 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/8725 (2013.01) [H01L 29/24 (2013.01); H01L 29/47 (2013.01); H01L 29/7802 (2013.01)] 3 Claims
OG exemplary drawing
 
2. A Schottky barrier diode, comprising:
a first semiconductor layer that comprises a Ga2O3-based single crystal and has a trench opening on one surface;
a second semiconductor layer that comprises a Ga2O3-based single crystal and is stacked on a surface of the first semiconductor layer on which the trench is not open;
an insulating film covering an inner surface of the trench;
a trench MOS barrier buried in the trench so as to be covered with the insulating film;
an anode electrode that forms a Schottky junction with the first semiconductor layer, is in contact with the trench MOS barrier and is configured so that a portion in contact with the first semiconductor layer comprises Mo or W; and
a cathode electrode connected to the second semiconductor layer,
wherein the first semiconductor layer is configured such that a turn-on voltage thereof is not less than 0.4 V and not more than 0.6 V.