US 11,923,448 B2
High voltage blocking III-V semiconductor device
Hyeongnam Kim, Chandler, AZ (US); Jens Ulrich Heinle, Villach (AT); Mohamed Imam, Chandler, AZ (US); Bhargav Pandya, Chandler, AZ (US); Ramakrishna Tadikonda, Torrance, CA (US); and Manuel Vorwerk, Villach (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Jan. 10, 2022, as Appl. No. 17/572,050.
Application 17/572,050 is a division of application No. 16/828,104, filed on Mar. 24, 2020, granted, now 11,251,294.
Prior Publication US 2022/0130987 A1, Apr. 28, 2022
Int. Cl. H01L 27/06 (2006.01); H01L 21/8252 (2006.01); H01L 27/085 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 21/8252 (2013.01); H01L 27/0605 (2013.01); H01L 27/085 (2013.01); H01L 27/088 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a base substrate of type IV semiconductor material comprising a rear surface and an upper surface opposite the rear surface;
first and second device areas that are electrically isolated from one another and each extend to the upper surface;
a first region of type III-V semiconductor material formed on the base substrate over the first device area;
a second region of type III-V semiconductor material formed on the base substrate over the second device area, the second region of type III-V semiconductor material being laterally electrically insulated from the first region of type III-V semiconductor material;
a first high-electron mobility transistor integrally formed in the first region of type III-V semiconductor material; and
a second high-electron mobility transistor integrally formed in the second region of type III-V semiconductor material,
wherein the first and second high-electron mobility transistors each comprise source and drain terminals and are each configured to control a conductive connection between the respective source and drain terminals; and
wherein the first and second high-electron mobility transistors are connected in series with the source terminal of the first high-electron mobility transistor connected to the drain terminal of the second high-electron mobility transistor,
wherein the source terminal of the first high-electron mobility transistor is electrically connected to the first device area, and
wherein the first device area is electrically isolated from a subjacent region of the base substrate by a first two-way voltage blocking device.