US 11,923,440 B2
Semiconductor devices and methods of manufacturing thereof
Shih-Yao Lin, New Taipei (TW); Chen-Ping Chen, Toucheng Township (TW); Kuei-Yu Kao, Hsinchu (TW); Hsiao Wen Lee, Hsinchu (TW); and Chih-Han Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/873,978.
Application 17/873,978 is a division of application No. 17/081,877, filed on Oct. 27, 2020, granted, now 11,522,073.
Prior Publication US 2022/0367672 A1, Nov. 17, 2022
Int. Cl. H01L 29/94 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/76 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6681 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a dielectric isolation structure disposed on the substrate and having a horizontal upper surface;
semiconductor fins disposed on the substrate, the semiconductor fins having semiconductor fin sidewalls;
a dummy fin having dummy fin sidewalls and disposed between the dielectric isolation structure and the semiconductor fins disposed on the substrate; and
a conducting gate disposed over the semiconductor fins and the dummy fin, the conducting gate contacting the dielectric isolation structure;
wherein an angle between the horizontal upper surface of the dielectric isolation structure and an adjacent of the semiconductor fin sidewalls of the fins disposed on the substrate is greater than 90 degrees, and an angle between the horizontal upper surface of the dielectric isolation structure and an adjacent of the dummy fin sidewalls is less than 90 degrees,
wherein the dummy fin includes a first dummy fin sublayer, a second dummy fin sublayer, and a third dummy fin sublayer.