| CPC H01L 29/41775 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53266 (2013.01); H01L 29/0665 (2013.01); H01L 29/41733 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/7851 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a gate structure comprising a gate electrode on a substrate;
a source/drain pattern on the substrate;
a source/drain contact electrically connected to the source/drain pattern;
a gate contact electrically connected to the gate electrode; and
a wiring structure electrically connected to the source/drain contact and the gate contact,
wherein the wiring structure comprises a first via plug, a second via plug, and a wiring line electrically connected to the first via plug and the second via plug,
wherein the first via plug comprises a single conductive film structure,
wherein the second via plug comprises a via barrier film, a lower via filling film, and an upper via filling film on the lower via filling film,
wherein the via barrier film does not overlap a side wall of the upper via filling film in a direction parallel to an upper surface of the substrate, and
wherein an upper surface of the via barrier film is lower than an upper surface of the lower via filling film with respect to the substrate.
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