US 11,923,421 B2
Integrated circuit structures having germanium-based channels
Siddharth Chouksey, Portland, OR (US); Glenn Glass, Portland, OR (US); Anand Murthy, Portland, OR (US); Harold Kennel, Portland, OR (US); Jack T. Kavalieros, Portland, OR (US); Tahir Ghani, Portland, OR (US); Ashish Agrawal, Hillsboro, OR (US); and Seung Hoon Sung, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 20, 2022, as Appl. No. 17/869,622.
Application 17/869,622 is a division of application No. 16/022,510, filed on Jun. 28, 2018, granted, now 11,437,472.
Prior Publication US 2022/0406895 A1, Dec. 22, 2022
Int. Cl. H01L 31/072 (2012.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 31/109 (2006.01)
CPC H01L 29/165 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit structure, the method comprising:
forming a trench in an isolation structure on a silicon substrate, the trench exposing a portion of the silicon substrate;
forming a lower silicon portion of a fin in the trench and on the exposed portion of the silicon;
forming an intermediate germanium portion of the fin in the trench and on the lower silicon portion of the fin;
forming a silicon germanium portion of the fin in the trench and on the intermediate germanium portion of the fin, wherein the intermediate germanium portion has a greater atomic concentration of germanium than the upper silicon germanium portion;
recessing the isolation structure to expose sidewalls of a portion of the fin; and
forming a gate stack on and along the exposed sidewalls of the portion of the fin.