US 11,923,416 B2
Semiconductor device having buried gate structure and method for fabricating the same
Seong-Wan Ryu, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jun. 1, 2022, as Appl. No. 17/829,581.
Application 17/829,581 is a continuation of application No. 16/919,368, filed on Jul. 2, 2020, granted, now 11,380,761.
Application 16/919,368 is a continuation of application No. 16/119,424, filed on Aug. 31, 2018, granted, now 10,741,643, issued on Aug. 11, 2020.
Claims priority of application No. 10-2018-0021240 (KR), filed on Feb. 22, 2018.
Prior Publication US 2022/0293734 A1, Sep. 15, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 21/324 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/0873 (2013.01) [H01L 21/324 (2013.01); H01L 29/4236 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and
a gate structure in the trench,
wherein the gate structure includes:
a gate dielectric layer formed on a bottom and sidewalls of the trench;
a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer;
a second gate electrode positioned over the first gate electrode;
a capping layer disposed over the second gate electrode; and
a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer,
wherein the dipole inducing layer extends between the capping layer and the gate dielectric layer, and
wherein a top surface of the dipole inducing layer is at a same level as a top surface of the first and second source/drain regions.