US 11,923,412 B2
Sub-fin leakage reduction for template strained materials
Rishabh Mehandru, Portland, OR (US); Stephen Cea, Hillsboro, OR (US); Anupama Bowonder, Portland, OR (US); Juhyung Nam, Hillsboro, OR (US); and Willy Rachmady, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 6, 2023, as Appl. No. 18/106,374.
Application 18/106,374 is a division of application No. 16/457,347, filed on Jun. 28, 2019, granted, now 11,600,696.
Prior Publication US 2023/0187492 A1, Jun. 15, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66818 (2013.01); H01L 29/7848 (2013.01); H01L 29/7854 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a transistor, comprising:
forming a fin and a dummy gate over a substrate, wherein the fin comprises:
a sub-fin layer;
a source region over the sub-fin layer;
a drain region over the sub-fin layer;
a channel region over the sub-fin layer, wherein the channel region is between the source region and the drain region; and
wherein the dummy gate comprises:
a first spacer over the fin proximate to an interface between the source region and the channel region;
a second spacer over the fin proximate to an interface between the drain region and the channel region; and
a dummy gate electrode between the first spacer and the second spacer;
exposing the channel region by removing the dummy gate electrode;
selectively etching the sub-fin layer below the channel region to form a cavity;
disposing an insulating material in the cavity;
disposing a gate dielectric over the channel region; and
disposing a gate electrode over the gate dielectric.