US 11,923,370 B2
Forksheet transistors with dielectric or conductive spine
Seung Hoon Sung, Portland, OR (US); Cheng-Ying Huang, Portland, OR (US); Marko Radosavljevic, Portland, OR (US); Christopher M. Neumann, Portland, OR (US); Susmita Ghose, Hillsboro, OR (US); Varun Mishra, Hillsboro, OR (US); Cory Weber, Hilsboro, OR (US); Stephen M. Cea, Hillsboro, OR (US); Tahir Ghani, Portland, OR (US); and Jack T. Kavalieros, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2020, as Appl. No. 17/030,226.
Prior Publication US 2022/0093647 A1, Mar. 24, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 21/84 (2006.01)
CPC H01L 27/1203 (2013.01) [H01L 21/84 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a dielectric spine;
a first transistor device comprising a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine;
a second transistor device comprising a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine;
an N-type gate structure on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the semiconductor channels of the first vertical stack of semiconductor channels; and
a P-type gate structure on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the semiconductor channels of the second vertical stack of semiconductor channels.