US 11,923,367 B2
Low resistance fill metal layer material as stressor in metal gates
Mrunal A Khaderbad, Hsinchu (TW); Ziwei Fang, Hsinchu (TW); Keng-Chu Lin, Ping-Tung (TW); and Hsueh Wen Tsau, Miaoli County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 22, 2022, as Appl. No. 17/870,964.
Application 17/870,964 is a continuation of application No. 16/717,433, filed on Dec. 17, 2019, granted, now 11,404,416.
Prior Publication US 2022/0384439 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/823431 (2013.01); H01L 21/82345 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a semiconductor substrate having an n-type transistor region and a p-type transistor region;
a first plurality of stacked semiconductor layers in the p-type transistor region and a second plurality of stacked semiconductor layers in the n-type transistor region;
a gate dielectric layer that wraps around each of the first and second plurality of stacked semiconductor layers;
a first metal gate in the p-type transistor region, the first metal gate having a work function metal layer and a first fill metal layer, wherein the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer wraps around and is in direct contact with the work function metal layer;
a second metal gate in the n-type transistor region, the second metal gate having a second fill metal layer that wraps around and is in direct contact with the gate dielectric layer, wherein the second fill metal layer applies a tensile stress over the second plurality of stacked semiconductor layers and includes a conductive material with a work function about equal to or lower than 4.3 eV;
a first gate contact feature over and directly contacting the first fill metal layer of the first metal gate;
a second gate contact feature over and directly contacting the second fill metal layer of the second metal gate; and
an interlayer dielectric layer on sidewalls of the first and the second gate contacts.