US 11,923,362 B2
Integrated circuit (IC) device
Myung-gil Kang, Suwon-si (KR); Beom-jin Park, Hwaseong-si (KR); Geum-jong Bae, Suwon-si (KR); Dong-won Kim, Seongnam-si (KR); and Jung-gil Yang, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 9, 2023, as Appl. No. 18/314,569.
Application 18/314,569 is a continuation of application No. 17/886,530, filed on Aug. 12, 2022, granted, now 11,676,964.
Application 17/886,530 is a continuation of application No. 17/150,712, filed on Jan. 15, 2021, granted, now 11,444,081, issued on Sep. 13, 2022.
Application 17/150,712 is a continuation of application No. 16/358,118, filed on Mar. 19, 2019, granted, now 10,930,649, issued on Feb. 23, 2021.
Claims priority of application No. 10-2018-0107892 (KR), filed on Sep. 10, 2018.
Prior Publication US 2023/0282642 A1, Sep. 7, 2023
Int. Cl. H01L 27/088 (2006.01); H01L 21/308 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/3086 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a fin-type active area protruding from a substrate and extending in a first horizontal direction;
a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween;
a second nanosheet disposed above the first nanosheet with a second separation space therebetween;
a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, the gate line having a sub-gate portion disposed in the second separation space;
a source/drain region disposed on the fin-type active area and in contact with the first nanosheet and the second nanosheet, a first level of a lower surface of the source/drain region being higher than a second level of the upper surface of the fin-type active area; and
a bottom insulation structure disposed in the first separation space,
wherein no portion of the gate line is disposed in the first separation space.