| CPC H01L 27/0207 (2013.01) [G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 23/5286 (2013.01); H01L 27/0925 (2013.01); H01L 29/0657 (2013.01); H01L 29/42392 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
standard cells disposed in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, wherein each of the standard cells comprises an active region, a gate structure that intersects the active region, source/drain regions on the active region on both sides of the gate structure, and interconnection lines electrically connected to the active region and the gate structure; and
filler cells between ones of the standard cells, wherein each of the filler cells comprises a filler active region and a filler gate structure that intersects the filler active region,
wherein the standard cells comprise first, second, and third standard cells in first, second, and third rows sequentially in the second direction,
wherein ones of the interconnection lines of the first standard cell are arranged with a first pitch in the second direction, ones of the interconnection lines of the second standard cell are arranged with a second pitch different from the first pitch in the second direction, and ones of the interconnection lines of the third standard cell are arranged with a third pitch different from the first and second pitches in the second direction.
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