US 11,923,343 B2
Semiconductor package and method of fabricating the same
Jaekyung Yoo, Seoul (KR); Jayeon Lee, Seongnam-si (KR); Jae-eun Lee, Hwaseong-si (KR); Yeongkwon Ko, Hwaseong-si (KR); Jin-woo Park, Seoul (KR); and Teak Hoon Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 29, 2022, as Appl. No. 18/059,747.
Application 18/059,747 is a continuation of application No. 17/140,241, filed on Jan. 4, 2021, granted, now 11,538,792.
Claims priority of application No. 10-2020-0061467 (KR), filed on May 22, 2020.
Prior Publication US 2023/0088032 A1, Mar. 23, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/13 (2013.01); H01L 23/3157 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a package substrate;
a cavity in the package substrate;
a first vent hole extending from a top surface of the package substrate to the cavity such that the first vent hole is in fluid communication with the cavity;
a second vent hole extending from a bottom surface of the package substrate to the cavity such that the second vent hole is in fluid communication with the cavity;
a first semiconductor chip mounted on the package substrate;
a second semiconductor chip mounted on the first semiconductor chip; and
a first under-fill layer filling a space between the package substrate and the first semiconductor chip,
wherein the first under-fill layer extending along the first vent hole, the cavity, and the second vent hole onto the bottom surface of the package substrate, and
wherein a width of the cavity is greater than a width of the first vent hole and a width of the second vent hole.