US 11,923,342 B2
Semiconductor package
Sanguk Han, Asan-si (KR); Chajea Jo, Yongin-si (KR); Hyoeun Kim, Cheonan-si (KR); and Sunkyoung Seo, Cheonan-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 28, 2022, as Appl. No. 17/705,872.
Application 17/705,872 is a continuation of application No. 16/742,341, filed on Jan. 14, 2020, granted, now 11,444,060.
Claims priority of application No. 10-2019-0083953 (KR), filed on Jul. 11, 2019.
Prior Publication US 2022/0216186 A1, Jul. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 24/13 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a lower semiconductor package,
wherein the lower semiconductor package includes:
a first semiconductor device including a first through electrode;
a second semiconductor device on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;
a lower molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device; and
an upper redistribution layer on the second semiconductor device and electrically connected to the second through electrode,
wherein an upper surface of the second through electrode is in contact with a lower surface of the upper redistribution layer, and
wherein the upper surface of the second through electrode and an upper surface of the lower molding member are coplanar with one another.