US 11,923,327 B2
Silicon photonic interposer with two metal redistribution layers
Michael Lee, Los Angeles, CA (US); John Paul Drake, St. Ives (GB); Ying Luo, San Diego, CA (US); Vivek Raghunathan, Mountain View, CA (US); and Brett Sawyer, Pasadena, CA (US)
Assigned to Rockley Photonics Limited, Altrincham (GB)
Appl. No. 17/596,252
Filed by ROCKLEY PHOTONICS LIMITED, Altrincham (GB)
PCT Filed Jun. 5, 2020, PCT No. PCT/EP2020/065712
§ 371(c)(1), (2) Date Dec. 6, 2021,
PCT Pub. No. WO2020/245416, PCT Pub. Date Dec. 10, 2020.
Claims priority of provisional application 62/858,894, filed on Jun. 7, 2019.
Prior Publication US 2022/0310540 A1, Sep. 29, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/16 (2023.01)
CPC H01L 24/06 (2013.01) [H01L 24/02 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 25/167 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/03914 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05015 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05169 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/05172 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05555 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/061 (2013.01); H01L 2224/06102 (2013.01); H01L 2224/06505 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for fabricating a silicon integrated circuit, the method comprising:
fabricating a first intermediate product, comprising:
a silicon substrate,
a first conductive layer on the silicon substrate, and
a dielectric layer on the first conductive layer;
etching a first opening and a second opening, into the dielectric layer, onto the first conductive layer;
forming a second conductive layer on the dielectric layer and on the first conductive layer in the first opening and in the second opening; and
removing a portion of the second conductive layer in a region including the second opening and a region surrounding the second opening.