US 11,923,294 B2
Interconnect structures of semiconductor device and methods of forming the same
Chia-Cheng Chou, Keelung (TW); Chung-Chi Ko, Nantou (TW); and Tze-Liang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 29, 2022, as Appl. No. 17/732,556.
Application 17/732,556 is a continuation of application No. 16/801,166, filed on Feb. 26, 2020, granted, now 11,373,947.
Prior Publication US 2022/0262725 A1, Aug. 18, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76807 (2013.01); H01L 23/528 (2013.01); C04B 2235/61 (2013.01); G01V 2210/6242 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An interconnect structure, comprising:
an etching stop layer over a substrate;
a dielectric layer on the etch stop layer;
an insert layer between the etching stop layer and the dielectric layer; and
a conductive line extending through the dielectric layer, the insert layer, and the etching stop layer; and
a via below the conductive line,
wherein a material of the insert layer is different from the dielectric layer and the etching stop layer
wherein a bottom surface of the insert layer is higher than a top surface of the via.