US 11,923,290 B2
Halogen treatment for NMOS contact resistance improvement
Siddharth Chouksey, Portland, OR (US); Gilbert Dewey, Beaverton, OR (US); Nazila Haratipour, Hillsboro, OR (US); Mengcheng Lu, Portland, OR (US); Jitendra Kumar Jha, Hillsboro, OR (US); Jack T. Kavalieros, Portland, OR (US); Matthew V. Metz, Portland, OR (US); Scott B Clendenning, Portland, OR (US); and Eric Charles Mattson, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 26, 2020, as Appl. No. 16/913,859.
Prior Publication US 2021/0407902 A1, Dec. 30, 2021
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/78 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 23/528 (2013.01); H01L 23/53223 (2013.01); H01L 23/53266 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a source region;
a drain region;
a semiconductor channel between the source region and the drain region;
a gate electrode over the semiconductor channel; and
interconnects to the source region and the drain region, wherein the interconnects comprise:
a barrier layer, wherein the barrier layer comprises titanium, aluminum, carbon, and fluorine, and wherein the fluorine is bonded to the titanium;
a metal layer; and
a fill metal.