US 11,923,270 B2
Semiconductor device
Tatsuya Kobayashi, Yokohama Kanagawa (JP); Fumiyoshi Kawashiro, Chiyoda Tokyo (JP); and Hisashi Tomita, Yokohama Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Sep. 2, 2021, as Appl. No. 17/465,703.
Claims priority of application No. 2020-159922 (JP), filed on Sep. 24, 2020.
Prior Publication US 2022/0093485 A1, Mar. 24, 2022
Int. Cl. H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/07 (2006.01)
CPC H01L 23/3735 (2013.01) [H01L 21/4807 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/40 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 25/072 (2013.01); H01L 25/50 (2013.01); H01L 2224/29239 (2013.01); H01L 2224/29247 (2013.01); H01L 2224/29255 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/40225 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73263 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/8384 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor chip having a first electrode on a first region of a first surface of the semiconductor chip and a second electrode on a second region of the first surface of the semiconductor chip;
a first metal plate;
a first conductive bonding sheet disposed between the first region of the first surface of the semiconductor chip and the first metal plate, and configured to bond the first electrode to the first metal plate;
a second metal plate;
a second conductive bonding sheet disposed between the second region of the first surface of the semiconductor chip and the second metal plate, and configured to bond the second electrode to the second metal plate;
a substrate having a metal film and a third conductive bonding sheet, wherein a third electrode is on a second surface of the semiconductor chip opposite the first surface, and the third electrode is bonded to the metal film through the third conductive bonding sheet;
a second semiconductor chip having a fourth electrode on a first region of a first surface of the second semiconductor chip and a fifth electrode on a second region of the first surface of the second semiconductor chip;
a third metal plate and a fourth metal plate;
a fourth conductive bonding sheet disposed between the first region of the first surface of the second semiconductor chip and the third metal plate, and configured to bond the fourth electrode to the third metal plate; and
a fifth conductive bonding sheet disposed between the second region of the first surface of the second semiconductor chip and the fourth metal plate, and configured to bond the fifth electrode to the fourth metal plate;
wherein a sixth electrode on a second surface of the second semiconductor chip opposite the first surface of the second semiconductor chip is bonded to a second metal film of the substrate through a sixth conductive bonding sheet;
wherein the first metal plate and the second metal plate are electrically connected by a first wiring, the second metal plate and the second metal film are electrically connected by a second wiring, and the third metal plate and the fourth metal plate are electrically connected by a third wiring.