US 11,923,244 B2
Subtractive metals and subtractive metal semiconductor structures
He Ren, San Jose, CA (US); Hao Jiang, San Jose, CA (US); Shi You, San Jose, CA (US); and Mehul B. Naik, San Jose, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Mar. 5, 2021, as Appl. No. 17/193,994.
Prior Publication US 2022/0285212 A1, Sep. 8, 2022
Int. Cl. H01L 21/768 (2006.01)
CPC H01L 21/76843 (2013.01) [H01L 21/76879 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A process for fabricating a semiconductor structure, comprising:
performing a degas operation on the semiconductor structure;
depositing a liner layer on the semiconductor structure;
performing a sputter operation on the liner layer of the semiconductor structure while applying a bias to the semiconductor structure via an alternating current to at least partially amorphize the liner layer; and
depositing, by physical vapor deposition, a metal layer on the liner layer, wherein:
the liner layer comprises Ti, Ta, TaN, or combinations thereof, and
a resistivity of the metal layer is about 30 μΩ·cm or less.