US 11,923,194 B2
Epitaxial blocking layer for multi-gate devices and fabrication methods thereof
Hsin-Che Chiang, Taipei (TW); Wei-Chih Kao, Taipei (TW); Chun-Sheng Liang, Changhua County (TW); and Kuo-Hua Pan, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Apr. 25, 2022, as Appl. No. 17/728,369.
Application 17/728,369 is a division of application No. 16/573,656, filed on Sep. 17, 2019, granted, now 11,315,785.
Prior Publication US 2022/0254623 A1, Aug. 11, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/0245 (2013.01) [H01L 21/02507 (2013.01); H01L 21/02587 (2013.01); H01L 29/0847 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate having a first lattice constant;
a dopant blocking layer disposed over the semiconductor substrate, wherein the dopant blocking layer has a second lattice constant different from the first lattice constant;
a buffer layer disposed over the dopant blocking layer, wherein the buffer layer has a third lattice constant different from the second lattice constant;
a plurality of channel members suspended over the buffer layer, wherein a top surface of the buffer layer is vertically spaced apart from a bottommost one of the plurality of channel members;
an epitaxial feature abutting the plurality of channel members, wherein a bottom portion of the epitaxial feature is below the top surface of the buffer layer; and
a gate structure wrapping each of the plurality of channel members.