US 11,923,042 B2
Apparatus, memory device, and method reducing clock training time
Sangwoo Kim, Seoul (KR); Younghoon Son, Yongin-si (KR); Seongheon Yu, Yongin-si (KR); Joungyeal Kim, Yongin-si (KR); and Chulung Kim, Seou (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 21, 2022, as Appl. No. 17/581,445.
Claims priority of application No. 10-2021-0087398 (KR), filed on Jul. 2, 2021.
Prior Publication US 2023/0005515 A1, Jan. 5, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/46 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 29/12015 (2013.01); G11C 29/46 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first signal pin configured to receive a data clock;
a second signal pin configured to transmit a read clock; and
a data clock circuit receiving the data clock and configured to
perform first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock in response to the first duty cycle monitoring,
perform second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock in response to the second duty cycle monitoring,
calculate an offset of the read clock in response to the timing-adjusted data clock, the first result and the second result, and
correct a duty error of the read clock using a read clock offset code derived in relation to the offset of the read clock,
wherein the data clock controls data write timing during a write operation executed by the memory device,
the data clock controls data read timing during a read operation executed by the memory device, and
the read clock controls communication of read data from the memory device.