US 11,923,040 B2
Apparatuses and methods including multilevel command and address signals
Kang-Yong Kim, Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 3, 2022, as Appl. No. 17/805,278.
Application 17/805,278 is a division of application No. 16/875,798, filed on May 15, 2020, granted, now 11,386,940.
Claims priority of provisional application 62/854,525, filed on May 30, 2019.
Prior Publication US 2022/0293147 A1, Sep. 15, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 8/18 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/106 (2013.01); G11C 7/1057 (2013.01); G11C 7/1087 (2013.01); G11C 8/10 (2013.01); G11C 8/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory configured to receive a plurality of multilevel command and address signals that represent a command structure including a command operand and memory addresses, the multilevel command and address signals having respective voltages corresponding to a non-binary value, wherein the memory includes:
a means for providing internal command signals representing the command operand based on the multilevel command and address signals, wherein the means for providing internal command signals comprises a latching means that provides bits of the command operand based on two of the multilevel command and address signals;
a means for providing internal address signals representing the memory addresses, the memory addresses including a plurality of bits represented by the internal address signals wherein the means for providing internal address signals comprises a decoding means that provides bits of the memory addresses based on two of the multilevel command and address signals; and
a means for performing memory operations based on the internal command signals on memory locations based on the internal address signals.