US 11,923,039 B2
Apparatuses and methods including multilevel command and address signals
Kang-Yong Kim, Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 3, 2022, as Appl. No. 17/805,275.
Application 17/805,275 is a division of application No. 16/875,798, filed on May 15, 2020, granted, now 11,386,940.
Claims priority of provisional application 62/854,525, filed on May 30, 2019.
Prior Publication US 2022/0293146 A1, Sep. 15, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 8/18 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/106 (2013.01); G11C 7/1057 (2013.01); G11C 7/1087 (2013.01); G11C 8/10 (2013.01); G11C 8/18 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a command and address bus;
a controller configured to provide multilevel command and address signals to the command and address bus, the multilevel command and address signals each having a respective voltage corresponding to one of at least three or more different values; and
a memory system coupled to the controller through the command and address bus, the memory system including a plurality of memories, each of the memories configured to receive the multilevel command and address signals and decode the multilevel command and address signals to represent binary values of a memory address, wherein each of the plurality of memories of the memory system are further configured to receive the multilevel command and address signals and decode the command and address signals to non-binary values of a command operand.