US 11,923,038 B2
Apparatuses and methods including multilevel command and address signals
Kang-Yong Kim, Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 3, 2022, as Appl. No. 17/805,272.
Application 17/805,272 is a division of application No. 16/875,798, filed on May 15, 2020, granted, now 11,386,940.
Claims priority of provisional application 62/854,525, filed on May 30, 2019.
Prior Publication US 2022/0293145 A1, Sep. 15, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 8/18 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/106 (2013.01); G11C 7/1057 (2013.01); G11C 7/1087 (2013.01); G11C 8/10 (2013.01); G11C 8/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an address decoder configured to receive address signals and provide decoded addresses;
a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations; and
a command/address input circuit configured to receive a plurality of multilevel command and address signals and provide output signals to the address decoder and the command decoder, wherein the multilevel command and address signals represent a command structure including a command operand to identify a memory command and further including memory address information to identify a memory location to which the memory command is directed,
wherein the command operand is represented by a first portion of the plurality of multilevel command and address signals and each of the multilevel command and address signals of the first portion represent a non-binary value, and wherein the address information is represented by a second portion of the plurality of multilevel command and address signals and the multilevel command and address signals of the second portion represent bits of memory address information.