US 11,923,035 B2
Pseudo dual port memory devices
Chan Ho Lee, Hwaseong-si (KR); Tae Min Choi, Seoul (KR); Jeong Kyun Kim, Hwaseong-si (KR); Hyeong Cheol Kim, Suwon-si (KR); Suk Youn, Seoul (KR); Ju Chang Lee, Suwon-si (KR); and Kyu Won Choi, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 10, 2022, as Appl. No. 17/668,760.
Claims priority of application No. 10-2021-0061423 (KR), filed on May 12, 2021; application No. 10-2021-0061801 (KR), filed on May 13, 2021; and application No. 10-2021-0104638 (KR), filed on Aug. 9, 2021.
Prior Publication US 2022/0366944 A1, Nov. 17, 2022
Int. Cl. G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/06 (2013.01) [G11C 7/1012 (2013.01); G11C 7/1048 (2013.01); G11C 7/1063 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A pseudo dual port memory device comprising:
a memory cell;
a pair of bit lines connected to the memory cell;
a write driver;
a sense amp;
a column multiplexer which is connected to the bit lines and configured to receive a write multiplexer control signal and a read multiplexer control signal, the column multiplexer configured to connect the bit lines to the write driver in response to the write multiplexer control signal and configured to connect the bit lines to the sense amp in response to the read multiplexer control signal;
a precharge control signal generation circuit which is connected to the column multiplexer and configured to generate a precharge control signal on the basis of the write multiplexer control signal and the read multiplexer control signal; and
a bit line precharge circuit which is connected to the precharge control signal generation circuit and the pair of bit lines and configured to precharge the bit lines on the basis of the precharge control signal.