US 11,923,029 B2
Memory system
Marie Takada, Yokohama (JP); and Masanobu Shirakawa, Chigasaki (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 9, 2023, as Appl. No. 18/180,944.
Application 18/180,944 is a division of application No. 17/471,539, filed on Sep. 10, 2021, granted, now 11,636,914.
Claims priority of application No. 2021-047628 (JP), filed on Mar. 22, 2021.
Prior Publication US 2023/0223097 A1, Jul. 13, 2023
Int. Cl. G11C 29/42 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01); G11C 29/44 (2006.01); G11C 29/50 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/1201 (2013.01); G11C 29/18 (2013.01); G11C 29/4401 (2013.01); G11C 29/50004 (2013.01); G11C 2029/1202 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory system comprising:
a non-volatile memory device; and
a controller configured to execute an error correction process on first data read from a first area at a first address of the non-volatile memory device and determine a read level used for reading data at the first address according to a result of the correction process, wherein
the controller is configured to
execute the correction process on first frame data of the first data using an error correction circuit, and
when the correction process on the first frame data has failed, determine the read level based on estimated data in the error correction circuit.