US 11,923,020 B2
Memory device and memory system
Hiroyuki Ishii, Kanagawa (JP); Yuji Nagai, Kanagawa (JP); Makoto Miakashi, Kanagawa (JP); Tomoko Kajiyama, Kanagawa (JP); and Hayato Konno, Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 24, 2022, as Appl. No. 17/679,667.
Claims priority of application No. 2021-132851 (JP), filed on Aug. 17, 2021.
Prior Publication US 2023/0057303 A1, Feb. 23, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cell transistors configured to store a plurality of bit data, respectively;
a first word line connected to a plurality of first memory cell transistors among the plurality of memory cell transistors;
a controller configured to perform a loop process including repetition of a program loop, the program loop including a program operation and a first verification operation; and
a storage circuit configured to store status information,
wherein the controller is configured to:
perform the loop process, and then perform a second verification operation, and
store first status data relating to a result of the loop process and store second status data relating to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.