US 11,923,015 B2
Semiconductor storage device and data erasing method
Shinichi Oosera, Yokohama Kanagawa (JP); Sumito Ohtsuki, Yokohama Kanagawa (JP); Tomoki Higashi, Yokohama Kanagawa (JP); and Yuki Soh, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Feb. 28, 2022, as Appl. No. 17/682,968.
Claims priority of application No. 2021-153539 (JP), filed on Sep. 21, 2021.
Prior Publication US 2023/0087334 A1, Mar. 23, 2023
Int. Cl. G11C 16/16 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor storage device, comprising:
a plurality of strings each including a first select transistor, a plurality of memory cell transistors, and a second select transistor connected in series;
a plurality of word lines each connected to memory cell transistors in a same position across the plurality of strings;
a bit line connected in common to a first end of each of the plurality of strings;
a source line connected in common to a second end of each of the plurality of strings; and
a control circuit configured to perform an erase operation on plurality of strings, wherein
the control circuit is configured to adjust, for each of the plurality of strings, either an application time of a first voltage applied to a gate of the first select transistor of the respective string in the erase operation or a voltage level of the first voltage applied to the gate of the first select transistor of the respective string in the erase operation.