US 11,923,013 B2
Operation method of semiconductor storage device
Akihiro Imamoto, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Nov. 23, 2022, as Appl. No. 17/993,211.
Application 17/993,211 is a continuation of application No. 17/376,638, filed on Jul. 15, 2021, granted, now 11,538,528.
Claims priority of application No. 2020-186895 (JP), filed on Nov. 10, 2020.
Prior Publication US 2023/0082191 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G11C 16/10 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/3459 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An operation method of a semiconductor storage device that comprises a first memory die having a first memory plane including a plurality of first memory blocks and a second memory plane including a plurality of second memory blocks, the method comprises:
starting a first write sequence for one of the first memory blocks in response to a first command set designating the one of the first memory blocks; and
starting a second write sequence for one of the second memory blocks in response to a second command set designating the one of the second memory blocks, wherein at least part of the second write sequence is performed while the first write sequence is being performed.