US 11,922,998 B2
Memory device with global and local latches
Atul Katoch, Kanata (CA); and Sahil Preet Singh, Bangalore (IN)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 24, 2022, as Appl. No. 17/752,319.
Application 17/752,319 is a continuation of application No. 17/010,335, filed on Sep. 2, 2020, granted, now 11,361,818.
Claims priority of provisional application 62/908,075, filed on Sep. 30, 2019.
Prior Publication US 2022/0284949 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/418 (2006.01); G11C 11/412 (2006.01)
CPC G11C 11/418 (2013.01) [G11C 11/412 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory bank including a memory cell connected to a local bit line and a word line;
a first local data latch connected to the local bit line, the first local data latch having an enable terminal configured to receive a first local clock signal;
a first global data latch connected to the first local data latch by a global bit line, the first global data latch having an enable terminal configured to receive a global clock signal; and
a NOR gate including:
a first input connected to receive an output of the first local data latch;
a second input connected to the first local clock signal via an inverter; and
an output connected to the local bit line.