| CPC G11C 11/4093 (2013.01) [G11C 5/06 (2013.01); G11C 11/4074 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/4099 (2013.01)] | 20 Claims |
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1. A non-volatile memory device comprising:
a first semiconductor layer including a plurality of cell strings each having a plurality of memory cells, and a plurality of metal lines arranged above the plurality of memory cells, the plurality of metal lines extending in a first direction, and the plurality of metal lines including first bit lines adjacent to each other in a second direction, second bit lines adjacent to each other in the second direction, and a common source line tapping wire between the first bit lines and the second bit lines; and
a second semiconductor layer arranged below the first semiconductor layer in a vertical direction and including a page buffer circuit connected to the first bit lines and the second bit lines,
wherein the page buffer circuit includes:
first transistors arranged below the first bit lines in the vertical direction and electrically connected to the first bit lines;
second transistors arranged below the second bit lines in the vertical direction and electrically connected to the second bit lines; and
a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction,
wherein the plurality of cell strings are disposed between the first and second bit lines and a common source line,
wherein the common source line tapping wire is electrically connected to the common source,
wherein the page buffer circuit is arranged in a page buffer circuit region of the second semiconductor layer, and
wherein the first guard ring is arranged in the page buffer circuit region and applied with a bias voltage.
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