US 11,922,994 B2
Semiconductor device verifying signal supplied from outside
Chikara Kondo, Tokyo (JP)
Assigned to Longitude Licensing Limited, Dublin (IE)
Filed by LONGITUDE LICENSING LIMITED, Dublin (IE)
Filed on Jul. 25, 2022, as Appl. No. 17/872,771.
Application 17/872,771 is a continuation of application No. 17/140,439, filed on Jan. 4, 2021, granted, now 11,398,269.
Application 17/140,439 is a continuation of application No. 16/709,160, filed on Dec. 10, 2019, granted, now 10,885,969, issued on Jan. 5, 2021.
Application 16/709,160 is a continuation of application No. 15/903,666, filed on Feb. 23, 2018, abandoned.
Application 15/903,666 is a continuation of application No. 15/403,531, filed on Jan. 11, 2017, abandoned.
Application 15/403,531 is a continuation of application No. 14/836,315, filed on Aug. 26, 2015, granted, now 9,576,641, issued on Feb. 21, 2017.
Application 14/836,315 is a continuation of application No. 14/295,231, filed on Jun. 3, 2014, granted, now 9,123,434, issued on Sep. 1, 2015.
Application 14/295,231 is a continuation of application No. 13/618,834, filed on Sep. 14, 2012, granted, now 8,767,502, issued on Jul. 1, 2014.
Claims priority of application No. 2011-212143 (JP), filed on Sep. 28, 2011.
Prior Publication US 2022/0358986 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 7/24 (2006.01); G11C 11/4063 (2006.01); G11C 11/4076 (2006.01); G11C 11/4078 (2006.01); G11C 11/408 (2006.01); G11C 11/409 (2006.01); G11C 29/52 (2006.01); G11C 8/12 (2006.01)
CPC G11C 11/409 (2013.01) [G11C 7/24 (2013.01); G11C 11/4063 (2013.01); G11C 11/4076 (2013.01); G11C 11/4078 (2013.01); G11C 11/408 (2013.01); G11C 29/52 (2013.01); G11C 8/12 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for controlling a memory device comprising:
supplying a chip select signal to the memory device; and
supplying a first signal having a plurality of bits to the memory device after a lapse of a predetermined latency following supplying the chip select signal;
wherein the memory device detects occurrence of an error in the first signal;
wherein the memory device outputs an alert signal and prevents access to an internal memory array if an error is detected.