US 11,922,993 B2
Read-time overhead and power optimizations with command queues in memory device
Koichi Kawai, Yokohama (JP); Sundararajan Sankaranarayanan, Fremont, CA (US); Eric Nien-Heng Lee, San Jose, CA (US); and Akira Goda, Tokyo (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 11, 2023, as Appl. No. 18/095,646.
Application 18/095,646 is a continuation of application No. 17/318,579, filed on May 12, 2021, granted, now 11,568,921.
Prior Publication US 2023/0148018 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/12 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); G11C 11/56 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01)
CPC G11C 11/4085 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); G11C 11/5642 (2013.01); G11C 16/26 (2013.01); G11C 16/34 (2013.01); G11C 16/0483 (2013.01); G11C 2211/5642 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
an array of memory cells comprising a first word line coupled to at least a subset of the array of memory cells; and
control logic coupled to the first word line, the control logic to perform operations comprising:
detecting, within a queue, a first read command to read first data from a first page of the subset of the array and a second read command to read second data from a second page of the subset of the array;
causing a voltage applied to the first word line to move to a target value;
causing a page buffer to sense the first data from a first bit line coupled to the first page and to sense the second data from a second bit line coupled to the second page; and
causing the first word line to be discharged.