| CPC G11C 11/4085 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a memory cell array including a plurality of memory cells connected to a plurality of word lines;
a row address decoder configured to:
generate a plurality of main word line driving signals and a plurality of sub word line driving signals based on a row address,
based on an odd signal representing that a first main word line driving signal driving an odd word line is activated among the plurality of main word line driving signals being activated, generate a plurality of encoded sub word line driving signals for driving a target word line among the plurality of word lines by outputting the plurality of sub word line driving signals in a first order, and,
based on an even signal representing that a second main word line driving signal driving an even word line is activated among the plurality of main word line driving signals being activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order; and
a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level based on the plurality of main word line driving signals and the plurality of encoded sub word line driving signals.
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