US 11,922,990 B2
Memory devices configured to provide external regulated voltages
Matthew A. Prather, Boise, ID (US); and Thomas H. Kinsley, Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 2, 2020, as Appl. No. 16/838,473.
Application 16/838,473 is a continuation of application No. 16/109,520, filed on Aug. 22, 2018, granted, now 10,665,288.
Claims priority of provisional application 62/635,429, filed on Feb. 26, 2018.
Prior Publication US 2020/0234753 A1, Jul. 23, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4074 (2006.01); G06F 13/10 (2006.01); G06F 1/26 (2006.01); H02M 3/156 (2006.01)
CPC G11C 11/4074 (2013.01) [G06F 13/102 (2013.01); G06F 1/26 (2013.01); H02M 3/156 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a power supply configured to provide a supply voltage to a memory device,
the memory device including:
one or more external inputs configured to receive the supply voltage;
a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage;
one or more memories configured to receive the output voltage from the voltage regulator;
one or more external outputs configured to receive the output voltage from the voltage regulator and to supply the output voltage to one or more connected devices; and
the one or more connected devices, wherein the one or more connected devices are configured to receive the output voltage from the one or more external outputs and do not receive the supply voltage from the power supply,
wherein the voltage regulator comprises a power management integrated circuit (PMIC) that includes one or more registers configured to store information corresponding to the output voltage, wherein the output voltage comprises a plurality of output voltages, and wherein the information comprises a first order in which the plurality of output voltages are powered up, first delays corresponding to the first order, a second order in which the plurality of output voltages are powered down, and second delays corresponding to the second order.