| CPC G09G 3/3266 (2013.01) | 29 Claims |
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1. A scan driver comprising a plurality of stages, wherein each of the plurality of stages comprises:
a first node controller connected to an input terminal, a first clock terminal, and a first control node, wherein a start signal is applied to the input terminal, and a first clock signal is applied to the first clock terminal;
a second node controller connected to the first clock terminal, a first voltage input terminal, a second voltage input terminal, and a second control node, wherein a first voltage of a first voltage level is applied to the first voltage input terminal, and a second voltage of a second voltage level is applied to the second voltage input terminal;
a third node controller, which is connected between the first voltage input terminal and a second clock terminal and controls a voltage level of a third control node according to a voltage level of the second control node; and
a first output controller comprising a first pull-up transistor and a first pull-down transistor, wherein the first pull-up transistor is connected between the first voltage input terminal and a first output terminal and outputs a first gate control signal of the first voltage level to the first output terminal, and the first pull-down transistor is connected between the second voltage input terminal and the first output terminal and outputs a first gate control signal of the second voltage level to the first output terminal,
wherein the first pull-down transistor comprises a first gate and a second gate, and
a gate of the first pull-up transistor and the first gate of the first pull-down transistor are connected to the third control node or a node electrically connected to the third control node.
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