CPC G09G 3/2092 (2013.01) [G09G 3/3208 (2013.01); G09G 3/3275 (2013.01); G09G 3/36 (2013.01); G09G 3/3688 (2013.01); G09G 5/001 (2013.01); G09G 2300/043 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/08 (2013.01); G09G 2320/02 (2013.01)] | 18 Claims |
1. A timing controller suitable for receiving image data and a timing signal from a host system and outputting output data to a data driving circuit, comprising:
a scrambler configured to output scrambled image data by scrambling the image data;
a pattern detection unit configured to calculate a first unbalanced pattern count as a count of unbalanced patterns included in the image data and a second unbalanced pattern count as a count of unbalanced patterns included in the scrambled image data; and
an output data determination unit configured to determine output data by using the first unbalanced pattern count and the second unbalanced pattern count.
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