US 11,922,533 B2
Dynamically reducing latency in processing pipelines
Sau Yan Keith Li, San Jose, CA (US); Seth Schneider, San Jose, CA (US); Cody Robson, Portland, OR (US); Lars Nordskog, Corte Madera, CA (US); Charles Hansen, San Francisco, CA (US); and Rouslan Dimitrov, Santa Clara, CA (US)
Assigned to Nvidia Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Sep. 21, 2021, as Appl. No. 17/448,258.
Prior Publication US 2023/0087268 A1, Mar. 23, 2023
Int. Cl. G06T 1/20 (2006.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 9/3836 (2013.01); G06F 9/4881 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method comprising:
obtaining a weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel, wherein the plurality of frames are processed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage;
determining a first largest weighted average execution time associated with one of the plurality of execution stages; and
applying a delay to the initial execution stage prior to processing a first next frame, wherein the delay is substantially equivalent to a difference between the first largest weighted average execution time and an execution time of a previous frame in the initial execution stage of the plurality of execution stages.