US 11,922,306 B2
Tensor controller architecture
Harshit Khaitan, Fremont, CA (US); Ganesh Venkatesh, San Jose, CA (US); and Simon James Hollis, Redmond, CA (US)
Assigned to Meta Platforms, Inc., Menlo Park, CA (US)
Filed by Meta Platforms, Inc., Menlo Park, CA (US)
Filed on Dec. 28, 2020, as Appl. No. 17/135,521.
Prior Publication US 2022/0207345 A1, Jun. 30, 2022
Int. Cl. G06N 3/08 (2023.01); G06F 12/02 (2006.01)
CPC G06N 3/08 (2013.01) [G06F 12/0207 (2013.01); G06F 12/0215 (2013.01); G06F 12/023 (2013.01); G06F 2212/251 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A machine-learning accelerator system, comprising:
a plurality of controllers each configured to traverse a feature map with n-dimensions according to instructions that specify, for each of the n-dimensions, a respective traversal size, wherein each controller comprises:
a counter stack comprising a plurality of counters each associated with a respective dimension of the n-dimensions of the feature map, wherein each counter is configured to increment a respective count from a respective initial value to the respective traversal size associated with the respective dimension associated with that counter;
a plurality of address generators each configured to use the respective counts of the plurality of counters to generate at least one memory address at which a portion of the feature map is stored, wherein a particular address generator of the plurality of address generators is configured to generate signals for enabling or disabling logic stages of the machine-learning accelerator system; and
a dependency controller computing module configured to (1) track conditional statuses for incrementing the plurality of counters and (2) allow or disallow each of the plurality of counters to increment based on the conditional statuses.