| CPC G06N 3/065 (2023.01) [G11C 11/54 (2013.01)] | 6 Claims |
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1. A neuron device comprising:
a plurality of gate electrodes extending parallel to each other in a first direction and separated from each other in a second direction perpendicular to the first direction;
a plurality of drain electrodes extending parallel to each other in the first direction and separated from each other in the second direction;
a plurality of source lines arranged separate from and between the plurality of gate electrodes and the plurality of drain electrodes in a third direction perpendicular to the first direction and the second direction, extending parallel to each other in the second direction, and separated from each other in the first direction, wherein each of the plurality of source lines intersects each of the plurality of gate electrodes and each of the plurality of drain electrodes in a plan view from above the plurality of gate;
a dielectric layer formed between the plurality of gate electrodes and the plurality of source lines in the third direction at a plurality of intersections between the plurality of gate electrodes and the plurality of source lines; and
a semiconductor layer formed between the plurality of drain electrodes and the plurality of source lines in the third direction at a plurality of intersections between the plurality of drain electrodes and the plurality of source lines.
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