US 11,922,293 B2
Computing device, a system and a method for parallel processing of data streams
Igal Raichelgauz, Tel Aviv (IL); Karina Odinaev, Tel Aviv (IL); and Yehoshua Y. Zeevi, Haifa (IL)
Assigned to Cortica Ltd., Tel Aviv (IL)
Filed by Cortica Ltd., Tel Aviv (IL)
Filed on Sep. 16, 2019, as Appl. No. 16/571,416.
Application 16/571,416 is a continuation of application No. 14/175,569, filed on Feb. 7, 2014, abandoned.
Application 14/175,569 is a continuation of application No. 12/084,150, granted, now 8,655,801, issued on Feb. 18, 2014, previously published as PCT/IL2006/001235, filed on Oct. 26, 2006.
Claims priority of application No. 171577 (IL), filed on Oct. 26, 2005; and application No. 173409 (IL), filed on Jan. 29, 2006.
Prior Publication US 2020/0012927 A1, Jan. 9, 2020
Int. Cl. G06F 9/30 (2018.01); G06F 9/28 (2006.01); G06F 9/38 (2018.01); G06N 3/049 (2023.01); G06N 3/063 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 9/28 (2013.01); G06F 9/30101 (2013.01); G06F 9/3885 (2013.01); G06F 9/3897 (2013.01); G06N 3/049 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus for processing a data stream, comprising:
a processing unit comprising a plurality of computational cores, wherein each computational core is configured to receive an input data stream and provide a unique output data stream, wherein each computational core of the plurality of computational cores comprises a liquid section; wherein liquid sections of the plurality of computational cores comprises leaky-to-threshold units (LTUs) and coupling node units (CNUs) that are used for connecting LTUs; wherein weightings and decay times of the CNUs of the plurality of computational cores are randomly set to randomly connect the LTUs of the plurality of computational cores, wherein at least two of the plurality of computational cores operate in parallel;
an input interface configured to receive the input data stream and simultaneously provide the same received input data stream to each of the at least two of the plurality of computational cores; and
an output interface configured to simultaneously receive the output data from each of the at least two of the plurality of computational cores.