US 11,922,240 B2
Unit element for asynchronous analog multiplier accumulator
Ryan Boesch, Louisville, CO (US); Martin Kraemer, Mountain View, CA (US); and Wei Xiong, Mountain View, CA (US)
Assigned to Ceremorphic, Inc., San Jose, CA (US)
Filed by Ceremorphic, Inc., San Jose, CA (US)
Filed on Dec. 31, 2020, as Appl. No. 17/139,226.
Prior Publication US 2022/0207247 A1, Jun. 30, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06G 7/16 (2006.01); G06F 17/16 (2006.01); G06J 1/00 (2006.01); H03M 1/12 (2006.01)
CPC G06G 7/16 (2013.01) [G06F 17/16 (2013.01); G06J 1/00 (2013.01); H03M 1/12 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A unit element having a digital A input and a digital B input, the unit element comprising:
a plurality of AND-groups, each AND-group comprising a plurality of AND gates, each AND gate of each AND-group having one input coupled to a unique digital bit of the A input and the other AND gate inputs commonly coupled to a digital bit of the B input;
a plurality of analog charge lines, each analog charge line coupled to a respective output of an AND gate of each AND-group through a charge transfer capacitor of value C;
a charge summing unit comprising a plurality of charge summing capacitors, one terminal of each charge summing capacitor coupled to a respective analog charge line, the other terminals of the charge summing capacitors coupled to an input of an analog to digital converter;
each charge summing capacitor of the charge summing unit having a value Cs*2n where n is the order of the respective analog charge line and a value Cs is smaller than the value C;
and where the largest value of Cs is smaller than ⅛th of an accumulated capacitance of charge transfer capacitors associated with AND gates coupled to an associated analog charge line.