US 11,922,172 B2
Configurable reduced memory startup
Karunakara Kotary, Portland, OR (US); Pannerkumar Rajagopal, Bangalore (IN); Satish Muthiyalu, Bangalore (IN); and Rajesh Poornachandran, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 22, 2020, as Appl. No. 17/028,315.
Prior Publication US 2021/0026649 A1, Jan. 28, 2021
Int. Cl. G06F 9/4401 (2018.01); G06F 1/3212 (2019.01); G06F 9/445 (2018.01); G06F 9/451 (2018.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 12/0873 (2016.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 11/406 (2006.01)
CPC G06F 9/4403 (2013.01) [G06F 1/3212 (2013.01); G06F 9/44505 (2013.01); G06F 9/451 (2018.02); G06F 11/3037 (2013.01); G06F 11/3409 (2013.01); G06F 12/0873 (2013.01); G06F 13/1668 (2013.01); G06F 13/4081 (2013.01); G11C 11/40622 (2013.01)] 25 Claims
OG exemplary drawing
 
20. A method comprising:
enabling, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface;
disabling, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface;
generating a map between a system address space and a first set of banks in the first set of ranks; and
excluding a second set of banks in the first set of ranks from the map.