US 11,922,166 B2
Vector SIMD VLIW data path architecture
Timothy David Anderson, University Park, TX (US); Duc Quang Bui, Grand Prairie, TX (US); Mujibur Rahman, Plano, TX (US); Joseph Raymond Michael Zbiciak, San Jose, CA (US); Eric Biscondi, Roquefort-les-pin (FR); Peter Dent, Northamptonshire (GB); Jelena Milanovic, Antibes (FR); and Ashish Shrivastava, Plano, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 17, 2023, as Appl. No. 18/097,552.
Application 18/097,552 is a continuation of application No. 16/852,690, filed on Apr. 20, 2020, granted, now 11,556,338.
Application 16/852,690 is a continuation of application No. 14/327,084, filed on Jul. 9, 2014, granted, now 10,628,156, issued on Apr. 21, 2020.
Claims priority of provisional application 61/856,817, filed on Jul. 22, 2013.
Claims priority of provisional application 61/844,074, filed on Jul. 9, 2013.
Prior Publication US 2023/0168890 A1, Jun. 1, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30036 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30018 (2013.01); G06F 9/30021 (2013.01); G06F 9/30112 (2013.01); G06F 9/3893 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor device comprising:
a first register configured to store a first vector that includes a first set of elements;
a second register configured to store a second vector that includes a second set of elements;
a third register configured to store a third vector that includes a third set of elements;
a first arithmetic unit configured to compare each element of the first set of elements to a respective element of the second set of elements to produce a first set of comparison bits;
a second arithmetic unit configured to compare each element of the first set of elements to a respective element of the third set of elements to produce a second set of comparison bits; and
a predicate unit configured to determine whether each element of the first set of elements is within a range defined by the second vector and the third vector based on the first set of comparison bits and the second set of comparison bits.