US 11,922,133 B2
Processor and method for processing mask data
Rene Peyrard, Voiron (FR); Fabrice Romain, Rians (FR); Jean-Michel Derien, Grenoble (FR); and Christophe Eichwald, Sassenage (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR); and STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR); and STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Sep. 30, 2020, as Appl. No. 17/038,774.
Claims priority of application No. 1911348 (FR), filed on Oct. 11, 2019.
Prior Publication US 2021/0109711 A1, Apr. 15, 2021
Int. Cl. G06F 7/57 (2006.01); G06F 7/76 (2006.01)
CPC G06F 7/57 (2013.01) [G06F 7/764 (2013.01)] 23 Claims
OG exemplary drawing
 
12. A central processing unit (CPU) comprising:
an arithmetic and logic unit comprising:
an input masking circuit comprising:
an arithmetic-to-logic circuit comprising:
a complementary circuit configured to receive first arithmetic-masked input data, and to generate masked complementary data;
a first carry circuit configured to receive the first arithmetic-masked input data and first input masks, and to generate arithmetic carry digits; and
a first exclusive-OR circuit coupled to the complementary circuit and the first carry circuit, and configured to generate first logic-masked input data; and
a logic-to-arithmetic circuit comprising:
a second carry circuit configured to receive second logic-masked input data and second input masks, and to generate logic carry digits; and
a second exclusive-OR circuit coupled to the second carry circuit, and configured to receive the second logic-masked input data and to generate second arithmetic-masked input data;
an arithmetic circuit coupled to the input masking circuit, and configured to apply arithmetic operations to the first arithmetic-masked input data, the first input masks, the second arithmetic-masked input data, and the second input masks to generate intermediate arithmetic-masked result data and first intermediate result masks;
a logic circuit coupled to the input masking circuit, and configured to apply logic operations to the first logic-masked input data, the first input masks, the second logic-masked input data, and the second input masks to generate intermediate logic-masked result data and second intermediate result masks; and
an output masking circuit coupled to the arithmetic circuit and the logic circuit, and configured to generate final masked result data and final result masks;
wherein the arithmetic and logic unit is configured to keep the first arithmetic-masked input data, the first logic-masked input data, the second arithmetic-masked input data, the second logic-masked input data, the masked complementary data, the intermediate arithmetic-masked result data, the intermediate logic-masked result data, and the final masked result data masked throughout processing of the first arithmetic-masked input data, the first logic-masked input data, the second arithmetic-masked input data, the second logic-masked input data, the masked complementary data, the intermediate arithmetic-masked result data, the intermediate logic-masked result data, and the final masked result data in the arithmetic and logic unit.