US 11,922,130 B2
Optimization of arithmetic expressions
Mihir Choudhury, Jersey City, NJ (US); Ayesha Akhter, Austin, TX (US); Alexander Ivrii, Haifa (IL); and Robert Lowell Kanzelman, Rochester, MN (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 10, 2021, as Appl. No. 17/547,413.
Prior Publication US 2023/0185528 A1, Jun. 15, 2023
Int. Cl. G06F 7/50 (2006.01); G06F 5/01 (2006.01); G06F 7/32 (2006.01)
CPC G06F 7/50 (2013.01) [G06F 5/01 (2013.01); G06F 7/32 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A computer-implemented method for executing arithmetic operations via an arithmetic logic unit, comprising:
converting, by one or more processors, arithmetic operators in an arithmetic expression into adders, such that all arithmetic operators in the arithmetic expression are adders;
identifying, by one or more processors, a topological order of the adders in the arithmetic expression, wherein the topological order of the adders includes a first adder followed by a second adder, and further wherein bit indexes between the first adder and the second adder are misaligned;
merging, by one or more processors, the first adder and the second adder into a multi-operand adder based, at least in part, on:
shifting input and output operands of the first adder by a same value of the misalignment between the bit indexes between the first adder and the second adder during the merging; and
normalizing all bit indexes of the multi-operand adder such that the bit indexes of the multi-operand adder are non-negative;
converting, by one or more processors, the multi-operand adder to a compressor tree and a two-operand adder; and
performing, by one or more processors, the arithmetic expression based on the converted multi-operand adder.