US 11,922,105 B1
Computer-aided design tool for minimum gate count initialization
Ikenna Odinaka, Durham, NC (US); Sasikanth Manipatruni, Portland, OR (US); Darshak Doshi, Sunnyvale, CA (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Amrita Mathuriya, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Nov. 10, 2021, as Appl. No. 17/523,572.
Application 17/523,572 is a continuation of application No. 17/384,626, filed on Jul. 23, 2021, granted, now 11,748,537.
Int. Cl. G06F 30/327 (2020.01); G06F 18/22 (2023.01); G06F 30/3953 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 18/22 (2023.01); G06F 30/3953 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory machine-readable storage media having machine-readable instructions stored thereon that when executed cause one or more machines to perform a method of determining a minimum gate count for initializing search-based logic synthesis, the method comprising:
receiving a list of truth tables associated with a logic circuit;
determining whether a number of truth table outputs in the list of truth tables is equal to one;
initializing a list of uncorrelated truth table outputs from the list of truth tables if it is determined that the number of truth table outputs is greater than one, wherein the list of uncorrelated truth table outputs is initially empty; and
populating the list of uncorrelated truth table outputs, based on one or more properties of an output from the truth table outputs, to determine the minimum gate count.