US 11,922,066 B2
Stacked device communication
Thomas Vogelsang, Mountain View, CA (US); Michael Raymond Miller, Raleigh, NC (US); and Steven C. Woo, Saratoga, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jan. 14, 2022, as Appl. No. 17/576,529.
Claims priority of provisional application 63/140,165, filed on Jan. 21, 2021.
Prior Publication US 2022/0229601 A1, Jul. 21, 2022
Int. Cl. G06F 3/06 (2006.01); G11C 7/10 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0626 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G11C 7/1006 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit stack, comprising:
an external command/address (CA) interface to receive commands and addresses from a device external to the integrated circuit stack;
a set of stacked memory devices comprising memory cell circuitry, the set of stacked memory devices to receive, via a memory device CA interface, commands and addresses received by the integrated circuit stack via the external CA interface; and,
a processing device electrically coupled to, and stacked with, the set of stacked memory device to form a first device stack, the first processing device comprising at least one processing element, the first processing device to receive, via a processing device CA interface, the commands and addresses received by the integrated circuit stack via the external CA interface, the first processing device to, in response to a first mode setting command received via the processing device CA interface, determine whether the first mode setting command is directed to the processing device.