US 11,922,055 B2
Stack register having different ferroelectric memory element constructions
Jon D. Trantham, Chanhassen, MN (US); Praveen Viraraghavan, Chicago, IL (US); John W. Dykes, Eden Prairie, MN (US); Ian J. Gilbert, Chanhassen, MN (US); Sangita Shreedharan Kalarickal, Eden Prairie, MN (US); Matthew J. Totin, Excelsior, MN (US); Mohamad El-Batal, Superior, CO (US); and Darshana H. Mehta, Shakopee, MN (US)
Assigned to SEAGATE TECHNOLOGY LLC, Fremont, CA (US)
Filed by Seagate Technology LLC, Fremont, CA (US)
Filed on Apr. 27, 2022, as Appl. No. 17/730,345.
Claims priority of provisional application 63/201,395, filed on Apr. 28, 2021.
Prior Publication US 2022/0350523 A1, Nov. 3, 2022
Int. Cl. G11C 11/22 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 11/22 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A ferroelectric stack register memory comprising:
a first arrangement of ferroelectric memory cells (FMEs) having a first construction arranged to provide a first number of cache lines adapted to respectively receive a corresponding first number of data entries from a processor;
a second arrangement of FMEs having a different, second construction arranged to provide a second number of cache lines adapted to respectively receive a corresponding second number of data entries from the processor; and
a pointer mechanism configured to provide pointers to point to each of the respective first and second numbers of cache lines based on a time sequence of operation of the processor.