US 11,922,041 B2
Threshold voltage bin calibration at memory device power up
Steven Michael Kientz, Westminster, CO (US); and Chia-Yu Kuo, Hukou Town (TW)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 8, 2022, as Appl. No. 17/883,418.
Claims priority of provisional application 63/312,349, filed on Feb. 21, 2022.
Prior Publication US 2023/0266904 A1, Aug. 24, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0644 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
identifying, by a processing device, a set of memory pages that have been programmed within a time window;
determining, for each voltage offset bin of a plurality of voltage offset bins, a corresponding value of a data state metric produced by a memory access operation with respect to a memory page of the set of memory pages, wherein the memory access operation utilizes a voltage offset associated with the voltage offset bin;
identifying a subset of the plurality of voltage offset bins, such that memory access operations performed using the corresponding voltage offsets produced respective values of the data state metric that satisfy a predefined quality criterion;
selecting, among the subset of the plurality of voltage offset bins, a voltage offset bin that is associated with the lowest voltage offset; and
associating the set of memory pages with the selected voltage offset bin.